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 HD74HC78
Dual J-K Flip-Flops (with Preset, Common Clear and Common Clock)
REJ03D0553-0200 (Previous ADE-205-425) Rev.2.00 Oct 06, 2005
Description
This flip-flop is edge sensitive to the clock input and change state on the negative transition of the clock pulse. Each flip-flop has independent J, K, and preset inputs and Q and Q outputs. Two flip-flops are controlled by a common clear and a common clock. Preset and clear are independent of the clock and accomplished by a low logic level on the corresponding input.
Features
* * * * * * High Speed Operation: tpd (Clock to Q) = 20 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 A max Low Quiescent Supply Current: ICC (static) = 2 A max (Ta = 25C) Ordering Information
Part Name HD74HC78FPEL HD74HC78RPEL Package Type SOP-14 pin (JEITA) SOP-14 pin (JEDEC) Package Code (Previous Code) PRSP0014DF-B (FP-14DAV) PRSP0014DE-A (FP-14DNV) Package Abbreviation FP RP Taping Abbreviation (Quantity) EL (2,000 pcs/reel) EL (2,500 pcs/reel)
Note: Please consult the sales office for the above package availability.
Function Table
Inputs Preset L H L H H H H H H H Clear H L L H H H H H H H L H Clock X X X J X X X L L H H X X X K X X X L H L H X X X L H Toggle No change No change No change Q H L H*1 No change H L Outputs Q L H H*1
H: High level L: Low level X: Irrelevant Note: 1. Q and Q will remain High as long as Preset and Clear are Low, but Q and Q are unpredictable, if Preset and Clear go High simultaneously.
Rev.2.00, Oct 06, 2005 page 1 of 6
HD74HC78
Pin Arrangement
CK 1 1PR 2 1J 3 VCC 4 CLR 5 2PR 6 2K 7 (Top view) K CK J CLR PR Q Q K CK J CLR PR Q Q
14 1K 13 1Q 12 1Q 11 GND 10 2J 9 2Q 8 2Q
Logic Diagram (1/2)
To Other FF
PR CLR J K # CK CK # CK # CK CK CK CK # CK
Q Q
CK
CK # CK
CK
CK
To Other FF
Rev.2.00, Oct 06, 2005 page 2 of 6
HD74HC78
Absolute Maximum Ratings
Item Supply voltage range Input / Output voltage Input / Output diode current Output current VCC, GND current Power dissipation Symbol VCC Vin, Vout IIK, IOK IO ICC or IGND PT Ratings -0.5 to 7.0 -0.5 to VCC +0.5 20 25 50 500 Unit V V mA mA mA mW
Storage temperature Tstg -65 to +150 C Note: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of which may be realized at the same time.
Recommended Operating Conditions
Item Supply voltage Input / Output voltage Operating temperature Input rise / fall time Note:
*1
Symbol VCC VIN, VOUT Ta tr , tf
Ratings 2 to 6 0 to VCC -40 to 85 0 to 1000 0 to 500
Unit V V C ns
Conditions
VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V
0 to 400 1. This item guarantees maximum limit when one input switches. Waveform: Refer to test circuit of switching characteristics.
Electrical Characteristics
Item Input voltage Symbol VCC (V) VIH 2.0 4.5 6.0 2.0 4.5 6.0 Output voltage VOH 2.0 4.5 6.0 4.5 VOL 6.0 2.0 4.5 6.0 4.5 6.0 Input current Quiescent supply current Iin ICC 6.0 6.0 Min 1.5 3.15 4.2 -- -- -- 1.9 4.4 5.9 4.18 5.68 -- -- -- -- -- -- -- Ta = 25C Typ Max -- -- -- -- -- -- 2.0 4.5 6.0 -- -- 0.0 0.0 0.0 -- -- -- -- -- -- -- 0.5 1.35 1.8 -- -- -- -- -- 0.1 0.1 0.1 0.26 0.26 0.1 2.0 Ta = -40 to+85C Unit Min Max 1.5 3.15 4.2 -- -- -- 1.9 4.4 5.9 4.13 5.63 -- -- -- -- -- -- -- -- -- -- 0.5 1.35 1.8 -- -- -- -- -- 0.1 0.1 0.1 0.33 0.33 1.0 20 IOL = 4 mA IOL = 5.2 mA A Vin = VCC or GND A Vin = VCC or GND, Iout = 0 A V V Vin = VIH or VIL IOH = -20 A V Test Conditions
VIL
V
IOH = -4 mA IOH = -5.2 mA Vin = VIH or VIL IOL = 20 A
Rev.2.00, Oct 06, 2005 page 3 of 6
HD74HC78
Switching Characteristics (CL = 50 pF, Input tr = tf = 6 ns)
Ta = 25C Item Maximum clock frequency Propagation delay time Symbol VCC (V) fmax 2.0 4.5 6.0 tPLH, tPHL 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 Pulse width tw 6.0 2.0 4.5 6.0 Setup time tsu 2.0 4.5 6.0 2.0 4.5 6.0 Removal time trem 2.0 4.5 6.0 2.0 4.5 6.0 Cin -- Min -- -- -- -- -- -- -- -- -- -- -- -- 80 16 14 100 20 17 5 5 5 100 20 17 -- -- -- -- Typ -- -- -- -- 20 -- -- 18 -- -- 18 -- -- 8 -- -- 2 -- -- -1 -- -- 0 -- -- 5 -- 5 Max 6 30 35 150 30 26 140 28 24 140 28 24 -- -- -- -- -- -- -- -- -- -- -- -- 75 15 13 10 Ta = -40 to +85C Min -- -- -- -- -- -- -- -- -- -- -- -- 100 20 17 125 25 21 5 5 5 125 25 21 -- -- -- -- Max 5 24 28 190 38 33 175 35 30 175 35 30 -- -- -- -- -- -- -- -- -- -- -- -- 95 19 16 10 pF ns Preset or Clear to Clock ns J or K to Clock ns Preset to Q or Q ns Clock to Q or Q Unit MHz Test Conditions
ns
Clear to Q or Q
ns
Preset, Clear, Clock
Hold time
th
ns
Clock to J or K
Output rise/fall time Input capacitance
tTLH, tTHL
ns
Test Circuit
VCC VCC
Output
See Function Table
Input Pulse generator Zout = 50 Input Pulse generator Zout = 50
Preset Clock J K Clear Q CL = 50 pF Q CL = 50 pF Output
Note: C L includes the probe and jig capacitance.
Rev.2.00, Oct 06, 2005 page 4 of 6
HD74HC78 Waveforms
* Waveform - 1
tr
90 %
tf t w (L) VCC
50 % 10 % 50 %
Clock
10 %
50 %
50 %
t w (H)
0V t THL
90 % 50 % 10 %
t TLH
90 % 50 % 10 %
VOH VOL
Q or Q t PLH t PHL Q or Q
t PHL t PLH
90 % 50 % 10 % 50 % 10 %
VOH VOL
t THL
t TLH
* Waveform - 2
tf 90 % 50 % 10 % t w(clear) 90 % 50 % t PHL 90 % 50 % 10 % t PLH Q t THL 90 % 50 % 10 % t TLH Notes: 1. Input waveform: PRR 1 MHz, Zo = 50 , tr 6 ns, tf 6 ns 2. The output are measured one at a time with one transition per measurement. 50 % VOL t PHL VOH 10 % t w(preset) t PLH Q 50 % VOL tr 90 % 50 % 10 % tf tr 90 % 50 % VCC 0V VCC 0V
Clear
Preset
VOH
Rev.2.00, Oct 06, 2005 page 5 of 6
HD74HC78
Package Dimensions
JEITA Package Code P-SOP14-3.95x8.65-1.27 RENESAS Code PRSP0014DE-A Previous Code FP-14DNV MASS[Typ.] 0.13g
*1
D 8
F
14
NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
bp
*2
Index mark
HE
E
c
Reference Symbol
Dimension in Millimeters Min Nom 8.65 3.95 Max 9.05
Terminal cross section ( Ni/Pd/Au plating )
1 Z e
*3
D E A2
7 bp x M L1
A1 A bp b1 c c1
0.10
0.14
0.25 1.75
0.34
0.40
0.46
0.15
0.20
0.25
A
HE
0 5.80 6.10 1.27
8 6.20
A1
L
e x y
0.25 0.15 0.635 0.40
1
y
Detail F
Z L L 0.60 1.08
1.27
JEITA Package Code P-SOP14-5.5x10.06-1.27
RENESAS Code PRSP0014DF-B
Previous Code FP-14DAV
MASS[Typ.] 0.23g
*1
D 8
F
NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
14
bp
HE
E
Index mark
*2
c
Reference Symbol
Dimension in Millimeters Min Nom 10.06 5.50 Max 10.5
Terminal cross section ( Ni/Pd/Au plating )
1 Z e
*3
D E A2 A1 0.00
7 bp x M L1
0.10
0.20 2.20
A bp b1 c c
1
0.34
0.40
0.46
0.15
0.20
0.25
A
HE
0 7.50 7.80 1.27
8 8.00
A1
y L
e x y
0.12 0.15 1.42 0.50
1
Detail F
Z L L 0.70 1.15
0.90
Rev.2.00, Oct 06, 2005 page 6 of 6
Sales Strategic Planning Div.
Keep safety first in your circuit designs!
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.
RENESAS SALES OFFICES
Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2730-6071 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology (Shanghai) Co., Ltd. Unit2607 Ruijing Building, No.205 Maoming Road (S), Shanghai 200020, China Tel: <86> (21) 6472-1001, Fax: <86> (21) 6415-2952 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001 Renesas Technology Korea Co., Ltd. Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea Tel: <82> 2-796-3115, Fax: <82> 2-796-2145
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Colophon .3.0


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